Niobium- Last Process for Multi-Foundry-Compatible Wafer Level Processing of Superconducting Interposers

Superconducting interposers fabricated with standard “CMOS-compatible” materials such as AI, TiN and Ta have been realized. Circuits built out of such materials require an operating environment provided by a He dilution fridge due to low critical temperature (Tc). Moreover, typical metallic superconductors suffer from low critical current density (Ic). A higher current load passing through the superconductor (I>Ic) can cause the material to lose its superconductivity. This case, the metal becomes resistive and produces heat. One main problem associated with a dilution fridge is that the cooling power of the fridge is typically low, and it cannot remove the heat efficiently. As such, current electronic controls must be located a distance away from the qubits. Moreover, it is challenging to increase the density of superconducting qubits due to limited cable I/O. It is pertinent then to search for high Tc and Ic materials. In one instance, Nb and its alloys are potential candidates for wafer-level fabrication. However, these materials might pose contamination risks to existing foundry lines. To overcome such limitations, we have successfully demonstrated a superconducting interposer constructed using a mostly “CMOS-compatible” materials. Al and other CMOS-compatible materials are first processed followed by the processing of Nb. frontside fabrication while Nb is deposited at wafer backside to maximize contamination control. This will help to minimize the introduction of elemental contamination into the foundry line.

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Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909755
Primary Topic
3D IC and TSV technologies
Type
article
Field-Weighted Citation Impact
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article

Niobium- Last Process for Multi-Foundry-Compatible Wafer Level Processing of Superconducting Interposers

Simon Chun Kiat Goh, Ya-Ching Tseng, Daniel Lau, Yong Chyn Ng et al.
3D IC and TSV technologies
article

Niobium- Last Process for Multi-Foundry-Compatible Wafer Level Processing of Superconducting Interposers

Simon Chun Kiat Goh, Ya-Ching Tseng, Daniel Lau, Yong Chyn Ng, Norhanani Jaafar, Edwin Hang Tong Teo, Hongyu Li, Liyuan Liu, Jae Ok Yoo, Javier Ong, Nicholas Boon Leong Chua
article en

Abstract

Superconducting interposers fabricated with standard “CMOS-compatible” materials such as AI, TiN and Ta have been realized. Circuits built out of such materials require an operating environment provided by a He dilution fridge due to low critical temperature (Tc). Moreover, typical metallic superconductors suffer from low critical current density (Ic). A higher current load passing through the superconductor (I>Ic) can cause the material to lose its superconductivity. This case, the metal becomes resistive and produces heat. One main problem associated with a dilution fridge is that the cooling power of the fridge is typically low, and it cannot remove the heat efficiently. As such, current electronic controls must be located a distance away from the qubits. Moreover, it is challenging to increase the density of superconducting qubits due to limited cable I/O. It is pertinent then to search for high Tc and Ic materials. In one instance, Nb and its alloys are potential candidates for wafer-level fabrication. However, these materials might pose contamination risks to existing foundry lines. To overcome such limitations, we have successfully demonstrated a superconducting interposer constructed using a mostly “CMOS-compatible” materials. Al and other CMOS-compatible materials are first processed followed by the processing of Nb. frontside fabrication while Nb is deposited at wafer backside to maximize contamination control. This will help to minimize the introduction of elemental contamination into the foundry line.

Agency for Science, Technology and Research (SG), Institute of Microelectronics (SG)
National Science Foundation, United Arab Emirates
Openalex Percentile: Top 74%
3D IC and TSV technologies
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