Integration Module of Dual MOSFET Switching Circuit Using Embedded Silicon Fan-Out (eSiFO) Technology

In this paper, an innovative integration module for dual MOSFET switching circuits based on eSiFO technology is presented, which consists of two P-type MOSFET (PMOS) chips and two N-type MOSFET (NMOS) chips. The cavities formed on silicon wafer by ICP dry etching method, the double-sided electrode of MOSFET chips are attached into cavity and the micro-scale gap between chips and cavities is filled by epoxy PI material. The MOSFET pads were fanned out by redistributed layer (RDL) on surface and metallization plating on all sides, and then interconnected with the array BGA solder balls. The parasitic resistance of returning current path based on eSiFO technology is lower than the traditional WB packaging, which will be beneficial to reducing the power loss and reducing heat generation. Meanwhile, the above mentioned integration modules ensure exceptional thermal performance, the steady-state thermal simulation and tests show that temperatures consistently maintained below 50°C when subjected to a 10A electric current.

Authors

Institutions

Publication Details

Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909888
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Integration Module of Dual MOSFET Switching Circuit Using Embedded Silicon Fan-Out (eSiFO) Technology

Xiangou Zhang, Shuairong Deng, Wenbin Qiang, Xiangyu Sun et al.
Advancements in Semiconductor Devices and Circuit Design
article

Integration Module of Dual MOSFET Switching Circuit Using Embedded Silicon Fan-Out (eSiFO) Technology

Xiangou Zhang, Shuairong Deng, Wenbin Qiang, Xiangyu Sun, Zhenzhong Yang
article en

Abstract

In this paper, an innovative integration module for dual MOSFET switching circuits based on eSiFO technology is presented, which consists of two P-type MOSFET (PMOS) chips and two N-type MOSFET (NMOS) chips. The cavities formed on silicon wafer by ICP dry etching method, the double-sided electrode of MOSFET chips are attached into cavity and the micro-scale gap between chips and cavities is filled by epoxy PI material. The MOSFET pads were fanned out by redistributed layer (RDL) on surface and metallization plating on all sides, and then interconnected with the array BGA solder balls. The parasitic resistance of returning current path based on eSiFO technology is lower than the traditional WB packaging, which will be beneficial to reducing the power loss and reducing heat generation. Meanwhile, the above mentioned integration modules ensure exceptional thermal performance, the steady-state thermal simulation and tests show that temperatures consistently maintained below 50°C when subjected to a 10A electric current.

China Academy of Engineering Physics (CN)
Affordable and clean energy
Openalex Percentile: Top 74%
Advancements in Semiconductor Devices and Circuit Design
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Integration Module of Dual MOSFET Switching Circuit Using Embedded Silicon Fan-Out (eSiFO) Technology — Xiangou Zhang, Shuairong Deng, et al. · (2024) | TGRS Research Map | TGRS