Maximizing Productivity Through Bonding Sequence Optimization in the Chip on Wafer Process
This paper presents a novel approach for optimizing chip bonding processes in semiconductor manufacturing, aimed at reducing bonding time while maintaining high precision. The conventional bonding method is time-consuming as it does not account for the distance between the two bonding heads during the process. We proposed a new algorithm to resolve this inefficiency by minimizing unnecessary head movements and optimizing the bonding sequence. Simulations showed successful results, achieving an average time reduction of 0.84% across 100 random sample cases, demonstrating the effectiveness of this approach in improving bonding efficiency without hardware modifications. These findings offer significant potential for enhancing overall productivity in chip on wafer (CoW) process.
Authors
- Minwoo Rhee
- Jungchul Lee (ORCID: https://orcid.org/0000-0001-7880-8657)
- Bumki Moon
- Hyeonjun Yun
- Yunha Kim (ORCID: https://orcid.org/0000-0001-6713-1900)
- Oh-Hyun Kwon
- Byungjoon Lee (ORCID: https://orcid.org/0000-0002-4712-3919)
- Hyungin Cho (ORCID: https://orcid.org/0000-0001-9948-3660)
- Jin Hee Kim (ORCID: https://orcid.org/0000-0003-1204-7079)
- Jisu Kim (ORCID: https://orcid.org/0009-0000-6910-5976)
- Mingu Kang (ORCID: https://orcid.org/0000-0002-0837-7254)
- Young-Seok Jung (ORCID: https://orcid.org/0000-0001-8086-6928)
- Kwanghyun Cho (ORCID: https://orcid.org/0000-0002-9038-8541)
- Geewoong Joung
Institutions
- Samsung (South Korea) (KR)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909760
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00