Package Design Optimization of ED-FCCSP with Different Die Aspect Comparison to Prevent Void Issue

The microelectronics products of Flip Chip-Chip Scale Package (FCCSP) with more increasing challenges are faced to assure molding capability with rapid advances in flip chip technology such as decreasing stand-off height and bump pitch, especially when Molded Underfill (MUF) is used during transfer molding process. Generally, traditional FCCSP is with over mold structure to ensure molding capabilities. However, as the demand for electronic signal transmission increases, the heat dissipation capability of the traditional FCCSP (over mold) package is also getting more challenge due to it difficulty satisfied high thermal dissipation under high power requirements. Therefore, FCCSP with Exposed die structure (ED-FCCSP) can provide an option to greatly increase the heat dissipation capacity requirements. However, the ED-FCCSP with expose die structure to cause more side effect during molding problems from the structural design. Among those side effect, the external void issue along die edge during the molding process is the most common and difficult to solve problem of ED-FCCSP. To solve external void is most important thing of ED-FCCSP suffer challenges In this paper, 3D moldflow simulation software which can apply transfer molding process parameters is used. We will present ED-FCCSP with different die size to perform different moldflow pattern comparison to judge external void risk during molding process. From this study, we can conclude some results for improvement molding performance of ED-FCCSP during transfer molding process. The ED-FCCSP with suitable die size and keep die aspect ratio less than 1:1.5 structure can perform low external void risk due to mold compound could easily flow along die edge to well obtain encapsulation package. In addition, ED-FCCSP package with low viscosity compound also performs well melt-front flow to reduce external void risk.