Process Optimization to Improve Electrical Performance of Aluminum Filled Via-Last TSV for BSI Applications
Low resistance and leakage current are crucial for reliable electrical interconnections, but these properties become increasingly difficult to maintain as bandwidth scaling leads to increase interconnection layers and reduced feature sizes This paper investigates the improvement of resistance in the via-last integration process by optimizing key processing steps. Use of a Titanium layer as a barrier during high-temperature Aluminum deposition improved the continuity with a reduced surface roughness, leading to lower resistivity. Additionally, the use of a mega-sonic NE14 cleaning process effectively removed the post-etch aluminum residues, further enhancing electrical performance more than 50%.
Authors
- Ting Ta
- Hong Yu Li
- Jun Wei Javier Ong
- Jae Ok Yoo
Institutions
- Agency for Science, Technology and Research (SG)
- Institute of Microelectronics (SG)
Publication Details
- Published
- 2024-12-03
- DOI
- https://doi.org/10.1109/eptc62800.2024.10909964
- Primary Topic
- 3D IC and TSV technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00