Robustness Methodology for Next Generation Automotive Microcontroller Flip Chip Copper Pillar Technologies

Next generation eMobility for electrified, intelligent and connected vehicles, advanced driver-assistance system (ADAS), automotive E/E architectures and affordable artificial intelligence (AI) requires the highest standards in real-time execution, security and dependability of new generation of micro-controller. In this paper, we discuss stringent mission profile and reliability requirement required for next generation automotive applications which pose major challenges to the prevailing industry automotive microcontroller flip-chip chip scale package (FCCSP) package design, validation methodology and manufacturing for robust development methodologies and qualification. Flip chip copper pillar crack and backend of line inter-layer dielectrics (BEOL ILD) cracks along the weakest interface/layer are some of major reliability challenges for the next generation automotive microcontroller package concept. In this paper, we introduced a new package concept robustness validation using novel methodologies to investigate the mechanical load via the copper pillars into the BEOL stack and numerical model has been developed to enable agile, fast design cycle and robust validation for critical failures and optimization for flip chip copper pillar design and material selection and manufacturability. We discuss the design of a new test chip, QTC test flow and methodology, novel detection and physical analysis method for critical flip chip copper pillar failures coupled with numerical simulation model to enable agile and fast evaluation of several FCCSP package & material concepts, flip chip copper pillar interconnect designs and identify significant design factors for the optimization of 1st and 2nd level reliability, in particularly FCCSP crack robustness for flip chip copper pillar and BEOL ILD horizontal cracks along the weakest interface/layer which is the focus of our study in this paper.