Fabrication of c-Si Pillars on Glass Substrates for Terahertz Dielectric Metasurfaces Using Glass-Silicon Direct Bonding

This study employs a low thermal budget glass-to-silicon direct bonding process without interlayers to fabricate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$200\mu \mathrm{m}$</tex> thick crystalline silicon (c-Si) pillars processed on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300\text{mm}$</tex> glass substrates. The process demonstrated robust bonding integrity, with no chip-off even after rigorous backgrinding procedures. Comprehensive investigations were conducted on the selection of glass substrates, the impact of cleaning processes on the bonding interface, and the optimization of these cleaning protocols. Additionally, lithography and etching processes were optimized on blank silicon wafers prior to their application on glass-bonded wafers. Challenges associated with handling glass on electrostatic chucks (ESC) were also addressed. Following these optimizations, a detailed process flow was developed for fabricating thick silicon pillars with aspect ratio ranging of 1:2. Surface and interface analyses were performed using confocal scanning acoustic microscopy, optical/laser profilometry, and X-SEM inspections. This fabrication flow shows significant potential in the fields of advanced packaging, optoelectronics, microfluidics, MEMS, and terahertz (THz) technologies.

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Published
2024-12-03
DOI
https://doi.org/10.1109/eptc62800.2024.10909897
Primary Topic
Microwave Engineering and Waveguides
Type
article
Field-Weighted Citation Impact
0.00

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article

Fabrication of c-Si Pillars on Glass Substrates for Terahertz Dielectric Metasurfaces Using Glass-Silicon Direct Bonding

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Microwave Engineering and Waveguides
article

Fabrication of c-Si Pillars on Glass Substrates for Terahertz Dielectric Metasurfaces Using Glass-Silicon Direct Bonding

Prakash Pitchappa, Theodore E. Fong, Hemanth Kumar Cheemalamarri, Navab Singh, Niketh Nair, Arvind Sundaram, Vempati Srinivasa Rao, B.S.S. Chandra Rao, Ho Sze Jye Jacky
article en

Abstract

This study employs a low thermal budget glass-to-silicon direct bonding process without interlayers to fabricate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$200\mu \mathrm{m}$</tex> thick crystalline silicon (c-Si) pillars processed on <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300\text{mm}$</tex> glass substrates. The process demonstrated robust bonding integrity, with no chip-off even after rigorous backgrinding procedures. Comprehensive investigations were conducted on the selection of glass substrates, the impact of cleaning processes on the bonding interface, and the optimization of these cleaning protocols. Additionally, lithography and etching processes were optimized on blank silicon wafers prior to their application on glass-bonded wafers. Challenges associated with handling glass on electrostatic chucks (ESC) were also addressed. Following these optimizations, a detailed process flow was developed for fabricating thick silicon pillars with aspect ratio ranging of 1:2. Surface and interface analyses were performed using confocal scanning acoustic microscopy, optical/laser profilometry, and X-SEM inspections. This fabrication flow shows significant potential in the fields of advanced packaging, optoelectronics, microfluidics, MEMS, and terahertz (THz) technologies.

Agency for Science, Technology and Research (SG), Singapore Polytechnic (SG), Institute of Microelectronics (SG)
Agency for Science, Technology and Research
Openalex Percentile: Top 74%
Microwave Engineering and Waveguides
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