High Aspect Ratio >10 TSV Design and Integration Challenges and Solutions for the Multi Memory Stacking

Through silicon vias (TSVs) remains a critical technology for enabling 2.5D and 3D packaging [1], The TSVs process can be considered successful only when it is void-free. There are many factors that may affect the gap-filling of the TSVs, including the TSVs etching profile, copper seed condition by physical vapor deposition (PVD), the additives and process parameters of electrochemical plating (ECP), etc. Besides, the TSVs pattern density also plays an important role in TSVs copper filling. In this study, an ECP void issue caused by the low TSV pattern density will be discussed and the solution will be provided.