Resolving Key Issues in Very Thin Die Package Manufacturing

Semiconductor package miniaturization commonly involves reducing the die thickness. However, more package manufacturing problems are expected as die becomes very thin and small. This paper discusses key issues and solutions in very thin die package assembly. Finite element analysis (FEA) and experimental evaluations or design of experiments (DOE) were performed. Results indicated that die cracks were located at areas in contact with the die attach ejector pin as higher stress is induced during ejection of the die from the wafer tape. It was found that using optimized tooling designs (ejector pin, pickup tool, wafer tape) and robust die attach process parameters were able to eliminate die crack and other related issues. The findings of the study clearly show that key issues in very thin and small die package manufacturing could be resolved by tooling design and process parameter optimization. FEA stress analysis and DOE are important tools to come up with optimum tooling design and process window parameters.