Process Development of Twin 2 Die Stack Modules for Deep Learning Hardware Accelerator

The demand of more computational power drives the need of having more and more memory to process the ever-increasing data amount. As such, there is a need to pack more memory dies on the same modules. In conventional approaches, memory dies are stacked on top of each other and communicated either using bonding wires or through micro-bumps. The interconnects through the use of TSV/micro-bumps are prefer as it offered better performance in terms of shorter communication length, lesser electrical parasites and the opportunity of heat transfer by attaching heat spreader on top of the die. In this manuscript, we are proposing putting two sets of two die stack with micro-bumps on the same interposer to enable a low-profile package that can be housed in application whereby the z-spacing is limited.