The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~60$ </tex-math></inline-formula> mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T =4 K - 300 K) and multi-frequency (f =1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

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Publication Details

Journal
IEEE Electron Device Letters
Published
2025-03-11
DOI
https://doi.org/10.1109/led.2025.3549865
Citations
1
Primary Topic
Thin-Film Transistor Technologies
Type
article
Field-Weighted Citation Impact
0.73
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article

The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs

Subhali Subhechha, Hongwei Tang, S. Subramanian, Jan Van Houdt et al.
1 citations
IEEE Electron Device Letters
Thin-Film Transistor Technologies
0.73
article

The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs

Subhali Subhechha, Hongwei Tang, S. Subramanian, Jan Van Houdt, Daisuke Matsubayashi, Yiqun Wan, Attilio Belmonte, Michiel J. van Setten, Adrian Chasin, Nouredine Rassoul, Harold Dekkers, Gouri Sankar Kar, Yuchao Jiang, Valeri Afanasiev, Zhuo Chen, Jie Li, Dennis Lin
article en
1 citations

Abstract

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~60$ </tex-math></inline-formula> mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T =4 K - 300 K) and multi-frequency (f =1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

IEEE Electron Device LettersVol. 46(5)
IMEC (BE), KU Leuven (BE)
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Openalex Percentile: Top 31%
Thin-Film Transistor Technologies
0.73
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The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs — Subhali Subhechha, Hongwei Tang, et al. · IEEE Electron Device Letters (2025) | TGRS Research Map | TGRS