Gate Stack Engineering for Top-Tier Devices in Monolithic 3D Integration Using Laser Annealing

In this study, we propose an approach to relieve the mechanical stress in the gate stack of top-tier devices during the monolithic 3D (M3D) integration process. In the M3D process, selective laser annealing process has been actively adopted for the fabrication of top-tier devices in order to avoid possible adverse effects on pre-existing bottom-tier devices. However, the perpendicular irradiation direction during the laser annealing generates a vertical thermal gradient across the gate stack of top-tier MOS devices, resulting in unavoidable mechanical stress that is detrimental to device performance. In this work, we have demonstrated that inserting an Al2O3 layer in between the TiN gate electrode and the HfO2 gate dielectric can reduce the mechanical stress in the gate stack. This approach can reduce the residual mechanical stress in the gate stack by approximately 67%, resulting in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~49$ </tex-math></inline-formula>% reduction in interface state density (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{{ {it}}}$ </tex-math></inline-formula>) and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim ~20$ </tex-math></inline-formula>% improvement in carrier mobility.