An Ultra-Fast 460-mA Capacitorless DLDO Achieving 8-ns Recovery Time and 99.58% Current Efficiency

In this brief, a fully-integrated output-capacitorless digital low-dropout regulator (DLDO) is proposed utilizing the parallel proportional and integral (PI) controllers to achieve reduced voltage undershoot (ΔVsubREG/sub) and fast transient response time (TsubREC/sub). The proposed PI controllers are implemented with the self-shifting bidirectional shift registers (SS-SRs) in coarse-fine dual loops along with complimentary PMOS and NMOS power transistors in coarse switch array and small-sized PMOS only transistors in fine switch array. Complimentary connectionsBR/of PMOS and NMOS power transistors compensate for the load current (IsubLOAD/sub) to reduce the ΔVsubREG/sub, and smallsized PMOS reduces the steady-state voltage ripples. The proposed DLDO was designed and fabricated in a 65-nm CMOS process with an active area of 0.08 mm². Simulated results demonstrate that the proposed capacitor-less DLDO operates with an input voltage range of 0.7 V-1.2 V. For a load current step of 460 mA at VDD = 1.2 V, the proposed DLDO recovers a ΔVsubREG/sub of 74 mV within 8 ns achieving an efficient load regulation of 0.004 mV/mA with a peak current efficiency of 99.58 %.