A Novel Embedded Drain Dual‐Gate Tunnel Field Effect Transistor with Drain Dielectric Pocket for Suppressing Ambipolar Effect

This work investigates the influence of embedding the drain into the channel and adding a dielectric pocket (DP) layer at the interface between the drain and the channel of double‐gate silicon tunnel field effect transistor (TFET; DP‐HD‐HJ‐DGTFET) on the device performance. DP can inhibit the point tunneling in the channel region, thus suppressing the ambipolar behavior of the device. The characteristics of this device, such as on‐state current ( I on ), average subthreshold swing (SS), ambipolar current ( I Amb ), I on / I Amb ratio, are emphatically analyzed. The results are compared with those of traditional double‐gate TFET (DGTFET) and SiGe/Si heterojunction TFET with hetero‐gate‐dielectric (HD‐HJ‐DGTFET) to prove its superiority. In addition, the influence of the length ( L p ), thickness ( T p ) of the DPs, the thickness of the drain region ( T d ) and different dielectric materials on the performance of the DP‐HD‐HJ‐DGTFET devices is investigated. Simulation results demonstrate that under the optimized conditions, the DP‐HD‐HJ‐DGTFET exhibits a lower I Amb of 1.49 × 10 −13 A μm −1 , higher I on / I Amb ratio of 1.8 × 10 8 , and lower SS of 20 mV decade −1 . Finally, the gate‐drain capacitance ( C gd ), transconductance ( g m ), cutoff frequency ( f t ), and gain bandwidth product of the device are also investigated to understand its radio frequency performance.