FPGA-based Hardware Acceleration for Model Predictive Control of Power Electronic Converters

Model predictive control (MPC) has gained considerable attention in power electronics but the high computational demands preclude its embedded and real-time implementation. This paper presents a novel FPGA-based hardware acceleration approach for MPC implementation in power electronic converters, enabling real-time, embedded operation with a total processing time potentially less than 1 µs, effectively eliminating the computational bottleneck. Furthermore, a comprehensive design guideline of FPGA-based hardware acceleration is presented using a buck converter as example, including top architecture programming to bottom calculation kernels design. This FPGA-based hardware acceleration framework for MPC is versatile, offering potential applicability across a wide range of power electronic systems. Simulation and experimental results using a buck converter with 5-step prediction horizon validate the efficacy of this approach.

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Publication Details

Published
2024-11-03
DOI
https://doi.org/10.1109/iecon55916.2024.10905677
Citations
2
Primary Topic
Multilevel Inverters and Converters
Type
article
Field-Weighted Citation Impact
0.42
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article

FPGA-based Hardware Acceleration for Model Predictive Control of Power Electronic Converters

R. Mark Nelms, Zhengchen Guo
2 citations
Multilevel Inverters and Converters
0.42
article

FPGA-based Hardware Acceleration for Model Predictive Control of Power Electronic Converters

R. Mark Nelms, Zhengchen Guo
article en
2 citations

Abstract

Model predictive control (MPC) has gained considerable attention in power electronics but the high computational demands preclude its embedded and real-time implementation. This paper presents a novel FPGA-based hardware acceleration approach for MPC implementation in power electronic converters, enabling real-time, embedded operation with a total processing time potentially less than 1 µs, effectively eliminating the computational bottleneck. Furthermore, a comprehensive design guideline of FPGA-based hardware acceleration is presented using a buck converter as example, including top architecture programming to bottom calculation kernels design. This FPGA-based hardware acceleration framework for MPC is versatile, offering potential applicability across a wide range of power electronic systems. Simulation and experimental results using a buck converter with 5-step prediction horizon validate the efficacy of this approach.

Auburn University (US)
Affordable and clean energy
Openalex Percentile: Top 35%
Multilevel Inverters and Converters
0.42
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FPGA-based Hardware Acceleration for Model Predictive Control of Power Electronic Converters — R. Mark Nelms, Zhengchen Guo · (2024) | TGRS Research Map | TGRS