Evaluation of SiC JFET/Si-pMOS switch under high temperature operating life test and repetitive current limitation conditions for space applications
This work evaluates the performance of a composite switch (SiC JFETs - Si pMOS) under high temperature and high electrical stress conditions for use as overcurrent protection device in DC distribution systems. Four different SiC JFET references have been analyzed. Experimental results demonstrate robustness in all conditions.
Authors
- E. Maset (ORCID: https://orcid.org/0000-0002-8739-3796)
- G. Terol
- David Marroquí (ORCID: https://orcid.org/0000-0001-5742-7871)
- David Alcaraz Iranzo (ORCID: https://orcid.org/0000-0002-2141-569X)
- J. M. Blanes (ORCID: https://orcid.org/0000-0002-0082-4064)
- A. Garrigós (ORCID: https://orcid.org/0000-0002-5386-2179)
Institutions
- Universitat de Miguel Hernández d'Elx (ES)
- Universitat de València (ES)
Publication Details
- Published
- 2024-11-03
- DOI
- https://doi.org/10.1109/iecon55916.2024.10905788
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00