A hardware acceleration Framework of Reconfigurable Edge Modules for Convolutional Neural Networks

Edge computing exploits node devices situated in close proximity to terminals to deliver distributed computing services directly to users, with FPGAs serving as the predominant platform. With the amplification in volume and intricacy of deep learning models, effectively deploying these models on FPGA devices introduces substantial challenges. To counter this predicament, this paper introduces an FPGA-based hardware acceleration framework for reconfigurable edge devices tailored for Convolutional Neural Networks (CNNs). Initially, a method for dynamically quantizing network models is devised to markedly curtail model memory consumption. Subsequently, a meticulously engineered hardware acceleration unit is formulated to attain augmented computing parallelism via meticulous temporal redesign. Finally, model deployment on FPGA devices for inference verification is showcased utilizing fully connected and convolutional neural networks as exemplars. On the MNIST dataset, the FPGA inference unit attains remarkable accuracy and computational efficiency in comparison to CPUs and GPUs