A 0.8 V Bandgap Voltage Reference with High PSRR for Low-Dropout Voltage Regulator in 22nm FD-SOI

This paper presents an area-efficient 0.8 V current-mode bandgap reference (BGR) in 22nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process. Implementing the body bias technique allows for smaller device sizes while maintaining high performance across process, voltage, and temperature variations. A regulated cascode structure further minimizes the reference voltage variation. Post-layout simulations show a temperature coefficient (TC) of 34.6 ppm/<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sup>C between -40<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sup>C and 125<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sup>C while consuming 0.82 mW of power from a 1.8 V supply voltage. The proposed BGR demonstrates a power supply rejection ratio (PSRR) below -53.9 dB over the full frequency range and a noise spectral density of $16.5\mu {\text{V}}/\sqrt {Hz} $ at 10 Hz. The BGR is integrated with a low-dropout (LDO) voltage regulator, which combined have a chip area of 0.008316 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, offering reduced size compared to the present state-of-the-art untrimmed BGRs.