Compact modeling of layout parasitic effects on power MOSFET switching

This paper studies the effect of layout parasitics on the switching behavior of power MOSFETs using a distributed modeling approach. It uses Verilog-A compact models for individual transistor cells to access the impact of layout parasitics on device performance. Parameter values of the SPICE model are validated through comparisons with a TCAD model of a silicon split-gate trench MOSFET. The compact model for the distributed MOSFET network enables accurate analysis of gate signal delay times, in contrast to the conventional approach employing constant RC networks. The modeling technique is also used to investigate the internal current and power distribution across the device layout during turn-on and turn-off switching events.