Comprehensive performance analysis of CMOS and CNTFET based 8T SRAM cell

In recent years, carbon nanotube field effect transistor (CNTFET) has become an attractive alternative to silicon for designing high-performance, highly stable, and low-power SRAM (Static Random Access Memory). SRAM serves as a cache memory in computers and many portable devices. Carbon nanotubes (CNTs), because of their exceptional transport capabilities, outstanding thermal conductivities, and impressive current handling capacities, have demonstrated great potential as an alternative device to the standard CMOS (Complementary Metal-Oxide-Semiconductor). The SRAM cell design using CNTFET is being compared to SRAM cell designs built using traditional CMOS technology. This paper presents the comprehensive analysis of CMOS & CNTFET based 8T SRAM cell design. Because of the nanoscale size, ballistic transport, and higher carrier mobility of the semiconducting nanotubes in CNTFET, it is integrated into the 8T SRAM cell. The approach incorporates several nonidealities, including the presence of quantum confinement consequences in the peripheral and transverse prescriptions, acoustic and transparent photon diffraction in the region surrounding the channel, as well as the screening effects by parallel CNTs (Carbon Nanotube) in CNTFETs with multiple CNTs. By incorporating Stanford University CNTFET model in CADENCE (virtuoso) 32nm simulation, we have found that CNTFET SRAM cell is 4 times faster in terms of Write/Read delay and the Write/Read power delay product (PDP) value is almost 5 times lower compared to CMOS based SRAM. We have also analyzed the effect of temperature & different tube positions of CNTs on the performance evaluation of the 8T SRAM cell.