Influence of MOS Interface Property on Performance of Cryo-CMOS Devices

Cryogenic-CMOS (Cryo-CMOS) technology has attracted a lot of attention for large-scale integrated quantum computers. For an accurate design of cryo-CMOS circuits operating at 4 K, understanding the device performance at cryogenic temperatures is required. However, the performance of cryo-CMOS devices is significantly different from that of CMOS devices operating at room temperature, and it is difficult to reproduce the cryogenic current-voltage characteristics using existing models as is. In recent years, great efforts have been made to obtain a physical understanding of cryo-specific performance. This paper provides an overview of the operation of cryo-CMOS devices and presents recent progress on its physical understanding with a particular focus on the influence of the oxide/Si interface.