91.2% Efficiency Low Power Non-Inverting Buck-Boost Converter

Two architectures of high efficiency low power DC-DC noninverting buck-boost (NIB B) converter is presented in this paper. The first architecture is NIBB with voltage divider in the feedback circuit and the second architecture is using Type-III Compensator using Op Amp-RC architecture. Second architecture improves stability and achieves low settling time. Both the circuits are implemented on Cadence Virtuoso using a 45nm CMOS process. With a maximum output load current of 200 mA, both produce a consistent 0.8 V when the input voltage varies between 0.6 and 1 V at 1MHz switching frequency. The first architecture network achieves a peak efficiency of 91.2% when the load resister is 12 Ω and the output voltage ripples were maintained under 91 mV. Also, the settling time for the second architecture is improved from 12.5μs to 8.2μs transition from boost to buck mode and from 7.5μs to 6.9μs from buck to boost mode. Additionally, both the architectures can achieve effective load and line regulation.

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Published
2024-12-01
DOI
https://doi.org/10.1109/tencon61640.2024.10902863
Primary Topic
Advanced DC-DC Converters
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article
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article

91.2% Efficiency Low Power Non-Inverting Buck-Boost Converter

M S Sunita, Aditya Kumar Gupta
Advanced DC-DC Converters
article

91.2% Efficiency Low Power Non-Inverting Buck-Boost Converter

M S Sunita, Aditya Kumar Gupta
article en

Abstract

Two architectures of high efficiency low power DC-DC noninverting buck-boost (NIB B) converter is presented in this paper. The first architecture is NIBB with voltage divider in the feedback circuit and the second architecture is using Type-III Compensator using Op Amp-RC architecture. Second architecture improves stability and achieves low settling time. Both the circuits are implemented on Cadence Virtuoso using a 45nm CMOS process. With a maximum output load current of 200 mA, both produce a consistent 0.8 V when the input voltage varies between 0.6 and 1 V at 1MHz switching frequency. The first architecture network achieves a peak efficiency of 91.2% when the load resister is 12 Ω and the output voltage ripples were maintained under 91 mV. Also, the settling time for the second architecture is improved from 12.5μs to 8.2μs transition from boost to buck mode and from 7.5μs to 6.9μs from buck to boost mode. Additionally, both the architectures can achieve effective load and line regulation.

PES University (IN)
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Advanced DC-DC Converters
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91.2% Efficiency Low Power Non-Inverting Buck-Boost Converter — M S Sunita, Aditya Kumar Gupta · (2024) | TGRS Research Map | TGRS