High Performance Flow Table for 5G Core Networks Based on FPGA

Flow Tables play a crucial role in the architecture of smart network interface cards (smart NICs). Essentially, they are data structures that map incoming packets to specific actions or destinations based on predefined rules. In the 5G core network, with the explosive increase in User Equipment (UE) connections and the significant number of TCP connections per UE, the importance of Flow Tables has risen significantly to accommodate hundreds of millions of flows. To achieve both high capacity and processing speed for Flow Tables, this paper presents a design approach where flow entries are stored in Double Data Rate 4 Synchronous Dynamic Random Access Memory (DDR4 SDRAM), supplemented with a cache stored in Double Data Rate 4 Synchronous Dynamic Random-Access Memory (SRAM) for frequently used flows, utilizing the CLOCK algorithm for cache placement management. Additionally, we implement the cuckoo hashing algorithm to improve collision resolution within the Flow Table. Furthermore, by applying pipelining and parallel processing, we enhance the throughput of the lookup process. Validation and performance evaluation were conducted on the Xilinx Alveo U200 card, yielding outstanding results: at an FPGA clock frequency of 300 MHz, our implementation achieved a superior throughput of up to 50 million flows per second.