A 9.94dBm IIP3 Inductorless Differential Low Noise Amplifier for Geofencing Applications

An inductorless differential Low Noise Amplifier (LNA) with high linearity, designed for geofencing applications, is presented. The LNA incorporates gm-boosting, linearity optimization, and noise-cancelling stages. A complementary derivative superposition technique is used for gm-boosting, while a common-source noise-cancelling path is employed to implement the linearity enhancement stage. The design uses a differential structure for linearity optimization, addressing inherent stability issues associated with the technique. Implemented in 65nm technology, the LNA occupies a chip area of 0.037 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and achieves a noise figure (NF) of 3.03 dB, a peak gain of 16.78 dB, and an IIP3 linearity of 9.94 dBm, with a power consumption of 28 mW. The LNA demonstrates good stability and process variation tolerance.

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Publication Details

Published
2024-12-01
DOI
https://doi.org/10.1109/tencon61640.2024.10902739
Primary Topic
Radio Frequency Integrated Circuit Design
Type
article
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article

A 9.94dBm IIP3 Inductorless Differential Low Noise Amplifier for Geofencing Applications

Jefferson A. Hora, Gene Fe P. Palencia, Xi Zhu, Chris Miguel Retorta et al.
Radio Frequency Integrated Circuit Design
article

A 9.94dBm IIP3 Inductorless Differential Low Noise Amplifier for Geofencing Applications

Jefferson A. Hora, Gene Fe P. Palencia, Xi Zhu, Chris Miguel Retorta, Raf Rohan Villacarlos
article en

Abstract

An inductorless differential Low Noise Amplifier (LNA) with high linearity, designed for geofencing applications, is presented. The LNA incorporates gm-boosting, linearity optimization, and noise-cancelling stages. A complementary derivative superposition technique is used for gm-boosting, while a common-source noise-cancelling path is employed to implement the linearity enhancement stage. The design uses a differential structure for linearity optimization, addressing inherent stability issues associated with the technique. Implemented in 65nm technology, the LNA occupies a chip area of 0.037 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and achieves a noise figure (NF) of 3.03 dB, a peak gain of 16.78 dB, and an IIP3 linearity of 9.94 dBm, with a power consumption of 28 mW. The LNA demonstrates good stability and process variation tolerance.

University of Technology Sydney (AU), Mindanao State University – Iligan Institute of Technology (PH)
Affordable and clean energy
Openalex Percentile: Top 74%
Radio Frequency Integrated Circuit Design
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