CMOS Design Of Reconfigurable Data-Panning Algorithm Based Sorter for 8-Input, 8-Bit Digital Data Using the 0.35um Library

The aim of the study is to design a CMOS based data-panning algorithm sorter. It aims to design a reconfigurable circuit that allows user to select the number of data to be simulated inside the sorter. The design was able to simulate 8 inputs and be sorted from lowest to highest simultaneously after 8 clock cycles. It has also a minimum hardware component compared to the other data sorter algorithms in terms of multiplexers, data registers, and magnitude comparators. It uses 2*N multiplexers, N*(b+1) data registers, and N/2 magnitude comparators for N represents the number of inputs while B represents the number of bits of the inputs. The CMOS layout occupied an area of 1.35 sq. m., a power consumption of 555 mW and a frequency of 50KHz.