VLSI Implementation of Recursive CNNs with Multi-Scale Integration for Image Classification Improvement

This work proposes an innovative approach to improving image classification through the implementation of a recursive convolutional neural network (ReCNN) on a Very-large-scale integration (VLSI) chip. By integrating multiple scaling variations and employing a voting mechanism, the proposed ReCNN enhances the accuracy of image recognition. Notably, this enhancement is achieved with minimal modifications, requiring only the addition of a voting circuit to the original network architecture. The test chip developed in this research is fabricated using TSMC <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18\mu m$</tex> · process technology. It boasts a maximum operating frequency of 37.7MHz, consumes only 22.5mW of power, and occupies a compact area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2. 5mm^2$</tex> ‘, Impressively, the gate count of the voting circuit is a mere 1K, constituting just 1.4% of the total chip area. Experimental findings validate the efficacy of the ReCNN design, showcasing significant improvements in image classification accuracy while maintaining low power consumption.