Enhancing the Readout Speed of NP-H-CAM Using Clocked CMOS Inverters

An H-CAM (Content Addressable Memory with Hamming distance search function) is a specialized similarity search hardware. Previous papers proposed and studies NP-H-CAM (Non-Precharge-H-CAM) to reduce the power consumption. The power consumption issue of the NP-H-CAM was improved by adding a clocked CMOS inverters to each memory cell. But the NP-H-CAM using clocked CMOS inverters has an issue with the long readout time. In this paper, we insert our newly proposed the “SIS (CMOS Switch-Inverter-Switch) type” clocked CMOS inverters into the memory cells of the NP- H -CAM to enhance the readout speed by about 30% with increasing the power consumption by about 3%. We compare the readout speed of the proposed and conventional circuits using HSPICE simulation and show the advantages of the proposed NP-H-CAM in terms of the readout speed.