Optimizing Convolutional Image Processing on RISC-V Using Branch Prediction on FPGA

This paper explores the enhancement of convolutional image processing on a RISC-V based architecture through the implementation of branch prediction (BP) techniques. Con-volution, a critical operation in image processing, is essential for tasks such as edge detection, blurring, and feature extraction. Efficient execution of convolution operations, particularly in a RISC-V architecture, requires effective BP to minimize delays caused by conditional operations. This study presents the development of a 5-stage pipelined 32-bit RISC-V processor, integrated with a 2-bit saturating counter branch predictor using a Branch History Table (BHT). The efficiency of the RISC-V processor was evaluated by synthesizing and implementing it using Xilinx Vivado on the Kintex- 7 KC705 Evaluation Platform and testing with a convolution algorithm written in assembly language. Experimental results demonstrate that optimizing BP significantly improves the execution efficiency of convolution operations, making it a promising approach for advanced image processing applications.