A 13-Bit Resolution High Performance Time Domain Comparator Using Intermediate Buffer Based VCO
This paper presents a VCO-based time domain comparator using intermediate buffers. The proposed comparator provides high resolution and better speed at low input voltage differences. In the comparator, there are two different delay paths which have complementary connections. Depending on the value of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{ip}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{in}$</tex> one path will be faster than the other. In this comparator, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{ip}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{in}$</tex> provide the delay to the pulses generated by the close loop operation of the comparator. The faster pulse will overcome the slower pulse and the output will settle to a decision. This comparator deals in the time domain and consumes less energy for small input voltage differences as compared to the conventional comparator, mainly when the input difference is large. This comparator provides 13 bits resolution with a lower delay compared to EPC and it is 2.3x times faster than the conventional EPC
Authors
- Santanu Sarkar (ORCID: https://orcid.org/0000-0002-9284-5654)
- M A Baig (ORCID: https://orcid.org/0000-0002-5151-3354)
Institutions
- National Institute of Technology Rourkela (IN)
Publication Details
- Published
- 2024-12-01
- DOI
- https://doi.org/10.1109/tencon61640.2024.10902767
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00