A Generalized Constraint Learning and Transfer Methodology with Net-First Graph Neural Network and Selective Topological Search for Hierarchical Analog / Mixed-Signal Circuit Layout Synthesis

Achieving efficient and effective automation in hierarchical analog/mixed-signal (AMS) integrated circuit layout synthesis remains a significant challenge in the electronic design automation domain, due to the vast design space and diverse layout requirements. The state-of-the-art AMS layout automation tools, like ALIGN and MAGICAL-EDA, utilize constraints extracted by designers to address this challenge. This constraint extraction is, however, a problem on its own when the number of constraints gets larger and the designs become more complicated. Recently, graph neural network (GNN)-based methods have been explored to extract inter-symmetry constraints in analog circuits, although with limited accuracy and applicability for other constraint types on hierarchical AMS circuits. In this article, we propose a generalized constraint learning and transfer (CLT) framework that can address a generalized, wider range of constraints and offers a more accurate and robust CLT methodology for hierarchical AMS circuit layout synthesis. A generate-and-aggregate approach enhanced by net-first GNN (Nest-GNN) and selective topological search (SelecTS) algorithms is introduced to accurately and efficiently learn and transfer to a more generalized range of constraint, including symmetry, impedance matching, and grouping for both placement and routing (P&R). This framework is the first one, to the best of our knowledge, to transfer constraint types such as grouping and impedance matching, for P&R on hierarchical AMS circuits. Tested on hierarchical AMS circuits with up to 25 hierarchies, over 1,000 devices, and more than 500 nets, our framework achieves an average CLT F1 score of over 0.98 for all constraint types in an efficient way, outperforming the state-of-the-art CLT methods.