High Performance IIR Filter Design Based on Fast Multiplier

This paper presents an optimal new method to design infinite impulse response (IIR) digital filters through implementing and comparing various multiplier architectures in order to opt the best approach among them. The reason behind focussing on the multiplier unit belongs to its essential role in the performance of the IIR filters. Direct form II is the realization form opted to characterize the suggested IIR filter which is coded, using Quartus II software and subdued to gate level simulation on field programmable gate array (FPGA) kit board. The proposed IIR filter, whose architecture includes the binary coded decimal (BCD) involved in it, has gained the best outcomes. The BCD multiplier is compared to other multipliers such as: array multiplier, parallel multiplier with two-splitting of Booth and parallel circuits, Vedic multiplier and Mux-Multiplier which are implemented with the Cyclone IV GX FPGA kit platform. It was observed that BCD-multiplier has recorded the smallest logic elements (188) along with the fastest operation speed (282.8 MHz) and the lowest delay time (7.89 ŋSec) compared to other approaches. The IIR filter circuit designed with the BCD multiplier is programmed and implemented on the Cyclone IV GX FPGA kit platform. Depending on the obtained results, the IIR filter based BCD-multiplier has promising features that make it more attractive than IIR systems based on other multipliers. Moreover, these features make the IIR filter widely exploited in diverse electronic systems and devices such as: images and biomedical signal processing applications, communications and radar systems.