FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration

This work proposes a 64Kb fully reconfigurable SRAM compute-in-memory (CIM) macro for convolutional neural network (CNN) acceleration using a 65nm node. It supports operation up to 400 MHz. The fully digital operation of the proposed macro effectively removes the analog CIM design issues related to process variations, noise susceptibility, and data-conversion overhead. Hence, it offers no accuracy loss, high energy efficiency, and large area saving for computation. To support the digital computation, a new area-efficient Digital Processing Unit (DPU) is proposed which is equivalent to 8.75T per bit storage. Moreover, the proposed macro features full precision reconfigurability (1b to 8b) for both input and weight, and fully flexible input activation ranging from 1 to 64 parallel inputs. It makes the proposed macro feasible for different neural network topologies. Removing sense amplifiers (SAs) for the memory mode of the proposed design suggests additional area and power savings. The proposed CIM macro achieves an energy efficiency of 249.1TOPS/W and a throughput of 819.2 GOPS.

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Publication Details

Journal
IEEE Transactions on Circuits and Systems I Regular Papers
Published
2025-03-07
DOI
https://doi.org/10.1109/tcsi.2025.3547853
Citations
6
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
13.62
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article

FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration

Narendra Singh Dhakad, Vishal Sharma, Tony Tae-Hyoung Kim, Xin Zhang
6 citations
IEEE Transactions on Circuits and Systems I Regular Papers
Parallel Computing and Optimization Techniques
13.62
article

FlexDCIM: A 400 MHz 249.1 TOPS/W 64 Kb Flexible Digital Compute-in-Memory SRAM Macro for CNN Acceleration

Narendra Singh Dhakad, Vishal Sharma, Tony Tae-Hyoung Kim, Xin Zhang
article en
6 citations

Abstract

This work proposes a 64Kb fully reconfigurable SRAM compute-in-memory (CIM) macro for convolutional neural network (CNN) acceleration using a 65nm node. It supports operation up to 400 MHz. The fully digital operation of the proposed macro effectively removes the analog CIM design issues related to process variations, noise susceptibility, and data-conversion overhead. Hence, it offers no accuracy loss, high energy efficiency, and large area saving for computation. To support the digital computation, a new area-efficient Digital Processing Unit (DPU) is proposed which is equivalent to 8.75T per bit storage. Moreover, the proposed macro features full precision reconfigurability (1b to 8b) for both input and weight, and fully flexible input activation ranging from 1 to 64 parallel inputs. It makes the proposed macro feasible for different neural network topologies. Removing sense amplifiers (SAs) for the memory mode of the proposed design suggests additional area and power savings. The proposed CIM macro achieves an energy efficiency of 249.1TOPS/W and a throughput of 819.2 GOPS.

IEEE Transactions on Circuits and Systems I Regular PapersVol. 72(10)
Nanyang Technological University (SG), Indian Institute of Technology Indore (IN)
Affordable and clean energy
Openalex Percentile: Top 1%
Parallel Computing and Optimization Techniques
13.62
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