Hardware Implementation for O-RAN Block Floating Point Compression and Decompression Methods in 5G Base Station

In the era of rapidly advancing 5G networks, bandwidth limitation has become a critical concern for network manufacturers. Our research focuses on the practical implementation of BFP compression using Field-Programmable Gate Arrays (FPGAs) based on the Open Radio Access Network (O-RAN). Specifically, the paper concentrates on reducing the bit count of In-phase and Quadrature (IQ) samples from 16 bits down to 9 bits through the application of a 9-bit BFP compression technique. The system operates at a clock frequency of 390.625 MHz, tailored for a 25G bandwidth. Moreover, the system is capable of handling both floating-point and fixed-point numbers. This effort leads to an impressive compression ratio of 0.5833 per Physical Resource Block (PRB). To assess the effectiveness of the deployment, the Error Vector Magnitude (EVM) method is employed, providing accurate measurement of the compression's impact, yielding results of 0.310 and 0.625 for QPSK (Quadrature Phase Shift Keying) and 64 QAM (Quadrature Amplitude Modulation), respectively. This article not only tackles the issue of bandwidth conservation but also offers practical insights into its real-world implementation using FPGA technology. The compression system is described using hardware language and is executed on the Xilinx Zynq ZC-706 board.