Design and verification of AES cryptography algorithm on RISC-V

—The implementation of the Advanced Encryption Standard (AES) on RISC-V processors has gained attention for its potential in secure and efficient cryptographic operations. Researchers have explored hardware acceleration techniques, custom instruction set extensions, and vector-based optimizations to enhance performance. AES integration into RISC-V cores has demonstrated improvements in execution speed, energy efficiency, and memory footprint, making it suitable for IoT and embedded applications. Several studies propose hardware accelerators and co-processors that reduce encryption time while maintaining cryptographic security. Vector-based AES implementations fur- ther improve efficiency by leveraging parallel processing capa- bilities of modern RISC-V architectures. The introduction of custom AES instructions enables high-throughput encryption and decryption with minimal software overhead. FPGA-based AES accelerators have also been explored to enhance adaptability and flexibility in cryptographic applications. Experimental results in- dicate that RISC-V AES implementations outperform traditional software-based encryption in terms of speed and power con- sumption. The standardization of AES instruction set extensions in RISC-V continues to evolve, contributing to a more secure and efficient cryptographic ecosystem. This paper reviews recent advancements in AES integration with RISC-V, highlighting key performance metrics and optimization techniques. Index Terms—AES-128 Encryption, RISC-V Cryptographic Extensions, Hardware Acceleration, FPGA-based AES Co- processor.