Device and Circuit-Level Performance Assessment of Interface Trap Charges on III–V Heterojunction TFETs for Reliability

In this paper, an extensive performance assessment has been performed in order to analyze the reliability of Ga[Formula: see text] As[Formula: see text]Sb/In[Formula: see text] Ga[Formula: see text]As TiO 2 -based Dual Material Stacked Double Gate Heterojunction TFET (TiO 2 -DMSDG-HJTFET) in comparison to GaSb/Si HfO 2 -based Dual Material Stacked Double Gate Heterojunction TFET (HfO 2 -DMSDG-HJTFET) under the influence of interface trap charges (ITCs) at device as well as circuit-level for the first time. The impact of both the donor (positive interface charges) and acceptor (negative interface charges) present at the interface has been taken into consideration. The performance of the device is evaluated in terms of DC electrical parameters, analog/RF and linearity parameters. Further, the impact of ITCs on the performance at the circuit level is carried out through a resistive-load inverter with HfO 2 -DMSDG-HJTFET and TiO 2 -DMSDG-HJTFET, evaluating their DC and transient characteristics. In addition to this, the investigation has been extended for the shot noise analysis in the presence of ITCs. In this work, the simulation has been conducted using the Silvaco Technology Computer-Aided Design (TCAD) tool, while the assessment of device performance at the circuit level has been performed using HSPICE, which is an industry standard circuit simulator. The simulation results demonstrate that TiO 2 -DMSDG-HJTFET exhibits greater resilience to ITCs concerning DC and analog/RF performance compared to HfO 2 -DMSDG-HJTFET. Hence, TiO 2 -DMSDG-HJTFET can act as a reliable candidate for analog/RF integrated circuit design and low power switching applications.