10T SRAM Cell Based on Tri State Buffer with Enhancing Read Stability

With the development of the advanced semiconductor technology, static power dissipation and data stability have become significant concerns in Static Random Access Memory (SRAM). To deal with these problems, a tentransistor (10T) SRAM cell has been proposed in this work. This design incorporates a different read port using a tri-state buffer, which isolates the storing node from the read bit line hence improve the read stability. The Read Static Noise Margin (RSNM) of the proposed 10T SRAM cell shows improvements by factors of 2.16, 1.6, and 1.14 compared to the conventional 6T SRAM cell, 10T SRAM cell, and modified 10T SRAM cell respectively. Read delay is reduced by 5x over basic 6T SRAM cell, 4.1x over 10T SRAM and 2.8x over another 10T SRAM cell. Additionally, the proposed design demonstrates write stability comparable to that of other designs. The proposed SRAM cell has been designed in 28 nm CMOS Technology