RVCP: High-Efficiency RISC-V Co-Processor for Security Applications in IoT and Server Systems

Nowadays, cryptography plays an increasingly important role in computer system security. Accordingly, high-speed cryptography computing platforms are required to meet security needs. Unfortunately, existing RISC-V processors still can not support many types of algorithms with high hardware speed and efficiency. Therefore, this paper proposes a RISC-V Co-Processor (RVCP) architecture, applying three innovative ideas: high bandwidth internal buffer set integration, pipelining with resource-sharing units, and unified SHA-256/SHA-512/SM3 design to support the custom instruction set extensions to support many cryptographic algorithms with high speed and power efficiency. Real-time evaluation results on the ZCU102 FPGA system on chip show that RVCP consumes a total power of 4.2 W and utilizes 34,898 LUTs, 29,644 FFs, and 16 BRAMs at the frequency of 210 MHz. Moreover, RVCP shows latency improvements by 16.91 to 92.28 times compared to the conventional RISC-V design. When compared to the most powerful CPU implementations, RVCP provides 1.1 to 11.66 times better hardware efficiency. Notably, RVCP also achieves 1.14 to 50.58 times better throughput than related RISC-V work.