A Dual-Loop Capacitor-Less NMOS LDO with Transient Enhancement Based on Voltage Comparison

The paper presents an output capacitor-less Low Dropout Regulator(OCL-LDO) that combines dual-loop and transient enhancement based on voltage comparison to increase bandwidth and slew rate with low quiescent current of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$20\text{pA}$</tex> and small on-chip capacitance of 4.2pF. The LDO, implemented in the SMIC <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18\mu\mathrm{m}$</tex> BCD technology, is fully integrated without load capacitor. It achieves a linear regulation of 1.4mV/V and a load regulation of 9.8mV/A, and ensures undershoot and overshoot of 220mV and 197mV during <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{load}}$</tex> transitions between <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$100\text{pA}$</tex> and 100mA.