A Discrete-Time Delta-Sigma Modulator with Low Power and High Resolution

This article presents a discrete-time third-order three-bit delta-sigma modulator (DSM) with the cascade-of- integrators feedforward (CIFF) topology, specifically designed for biological signal conversion in wearable medical devices. Within this modulator, a two-step adder is employed to facilitate the precise addition of analog signals while simultaneously mitigating the design requirements for the operational amplifier. To address the nonlinearity in multi-bit digital-to- analog converters (DACs), the data weighting averaging (DWA) digital calibration circuit is implemented. According to the post- simulation results, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 111.3 dB over a 1 kHz signal bandwidth, with a sampling frequency of 1.024 MHz. It operates with a power consumption of 0.52 mW from a 1.8 V supply, resulting in a Schreier figure of merit (FoM) of 174.1 dB.

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Publication Details

Published
2024-10-26
DOI
https://doi.org/10.1109/cisp-bmei64163.2024.10906130
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.18
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article

A Discrete-Time Delta-Sigma Modulator with Low Power and High Resolution

Xiaofeng Yan, Shengxi Diao
1 citations
Analog and Mixed-Signal Circuit Design
0.18
article

A Discrete-Time Delta-Sigma Modulator with Low Power and High Resolution

Xiaofeng Yan, Shengxi Diao
article en
1 citations

Abstract

This article presents a discrete-time third-order three-bit delta-sigma modulator (DSM) with the cascade-of- integrators feedforward (CIFF) topology, specifically designed for biological signal conversion in wearable medical devices. Within this modulator, a two-step adder is employed to facilitate the precise addition of analog signals while simultaneously mitigating the design requirements for the operational amplifier. To address the nonlinearity in multi-bit digital-to- analog converters (DACs), the data weighting averaging (DWA) digital calibration circuit is implemented. According to the post- simulation results, the modulator achieves a peak signal-to-noise and distortion ratio (SNDR) of 111.3 dB over a 1 kHz signal bandwidth, with a sampling frequency of 1.024 MHz. It operates with a power consumption of 0.52 mW from a 1.8 V supply, resulting in a Schreier figure of merit (FoM) of 174.1 dB.

East China Normal University (CN)
Affordable and clean energy
Openalex Percentile: Top 49%
Analog and Mixed-Signal Circuit Design
0.18
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