PANDA: Adaptive Prefetching and Decentralized Scheduling for Dataflow Architectures
Dataflow architectures are considered promising architecture, offering a commendable balance of performance, efficiency, and flexibility. Abundant prior works have been proposed to improve the performance of dataflow architectures. Nevertheless, these solutions can be further improved due to the lack of efficient data prefetching and flexible task scheduling. In this article, we propose a novel dataflow architecture with adaptive p refetching an d d ecentr a lized scheduling (PANDA). First, we present an application-adaptive data prefetching method and on-chip memory microarchitecture designed to overlap memory access latency. Second, we introduce a decentralized dataflow scheduling approach and processing element (PE) microarchitecture aimed at improving hardware utilization. Experimental results show that in a wide range of real-world applications, PANDA attains up to 2.53× performance improvement and 1.79× energy efficiency improvement over the state-of-the-art dataflow architectures.
Authors
- Dongrui Fan (ORCID: https://orcid.org/0000-0001-5219-0908)
- Xiaochun Ye (ORCID: https://orcid.org/0000-0003-4598-1685)
- Zhihua Fan (ORCID: https://orcid.org/0000-0002-5950-7370)
- Xuejun An (ORCID: https://orcid.org/0009-0005-0494-6332)
- Wenming Li (ORCID: https://orcid.org/0000-0003-4069-2251)
- Shantian Qin (ORCID: https://orcid.org/0009-0007-0411-9366)
- Zhen Wang (ORCID: https://orcid.org/0009-0003-8853-9915)
Institutions
- Chinese Academy of Sciences (CN)
- Institute of Computing Technology (CN)
- University of Chinese Academy of Sciences (CN)
Publication Details
- Journal
- ACM Transactions on Architecture and Code Optimization
- Published
- 2025-03-06
- DOI
- https://doi.org/10.1145/3721288
- Citations
- 2
- Primary Topic
- Parallel Computing and Optimization Techniques
- Type
- article
- Field-Weighted Citation Impact
- 4.54