Hardware Acceleration-Based Privacy-Aware Authentication Scheme for Internet of Vehicles Using Physical Unclonable Function

Due to technological advancement, the advent of smart cities has facilitated the deployment of advanced urban management systems. This integration has been made possible through the Internet of Vehicles (IoV), a foundational technology. By connecting smart cities with vehicles, the IoV enhances the safety and efficiency of transportation. This interconnected system facilitates wireless communication among vehicles, enabling the exchange of crucial traffic information. However, this significant technological advancement also raises concerns regarding privacy for individual users. This paper presents an innovative privacy-preserving authentication scheme focusing on IoV using physical unclonable functions (PUFs). This scheme employs the k-nearest neighbor (KNN) encryption technique, which possesses a multi-multi searching property. The main objective of this scheme is to authenticate autonomous vehicles (AVs) within the IoV framework. An innovative PUF design is applied to generate random keys for our authentication scheme to enhance security. This two-layer security approach protects against various cyber-attacks, including fraudulent identities, man-in-the-middle attacks, and unauthorized access to individual user information. Due to the substantial amount of information that needs to be processed for authentication purposes, our scheme is implemented using hardware acceleration on an Nexys A7-100T FPGA board. Our analysis of privacy and security illustrates the effective accomplishment of specified design goals. Furthermore, the performance analysis reveals that our approach imposes a minimal communication and computational burden and optimally utilizes hardware resources to accomplish design objectives. The results show that the proposed authentication scheme exhibits a non-linear increase in encryption time with a growing AV ID size, starting at 5μs for 100 bits and rising to 39 μs for 800 bits. Also, the result demonstrates a more gradual, linear increase in the search time with a growing AV ID size, starting at less than 1 μs for 100 bits and rising to less than 8 μs for 800 bits. Additionally, for hardware utilization, our scheme uses only 25% from DSP slides and IO pins, 22.2% from BRAM, 5.6% from flip-flops, and 24.3% from LUTs.