A 38Mb/mm² 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology

This paper describes a 3nm-FinFET high-density SRAM compiler with an interface dual-rail (IDR) architecture to enable SoC operation down to 380mV, the lowest SRAM interface voltage reported to date. The SRAM achieves a density of 38Mb/mm2, the highest 1-port SRAM density reported to date. The lOR architecture enables the SRAM <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${V}_{{DD}}$</tex> interface to go as low as the shared SoC <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${V}_{{DD}}$</tex> standard logic, unrestricted by SRAM internal operations or the SRAM bitcell array supply voltage, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${V}_{{DDA}}$</tex> The lowest possible SoC power can be achieved by supporting the lowest possible standard logic operational <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${V}_{{DDMIN}}$</tex> without impacting SRAM functionality or yield. level-shifting performance and area penalties typical of dual-rail designs are minimized with the lOR architecture. Key design features include an extended-range level shifter (ERLS), an integrated input latch and ERLS, a clock buffer with hig <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">${h}$</tex> -voltage level-shift bypass, and an integrated output latch and level-shifter (LS). The SRAM compiler generates instances up to 1.3Mb capacity, which can be used for SoC memory applications such as a shared multi-CPU L3-data cache.