A Differential Series-Resonance CMOS VCO with Pole-Convergence Technique Achieving 202.1 dBc/Hz FoM_TA at 10MHz Offset

Voltage-controlled oscillators with ultra-low phase noise (PN) are extensively sought for various applications, such as high-speed wireless/wireline communications, high-speed ADC/DACs, etc. According to Leeson's formula (Fig. 19.5.1 top-left), achieving lower PN requires a larger <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{TANK}$</tex> or a smaller <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex>. Since the maximum <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{TANK}$</tex> is constrained by technology and minimum <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$L$</tex> is limited by the ‘small-inductor’ issue [1], the multicore technique can be employed. By coupling <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> VCO cores, the equivalent parallel resistance <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R_{P}$</tex> is scaled down by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex>, and the PN is improved by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10\log(N)$</tex>, while the FoM is kept unchanged ideally. However, as the number of cores increases, so do the silicon area and potential mismatch among cores, while the design complexity, such as the power-delivery network, also becomes more challenging. Using series-resonance VCOs (SR-VCOs) offers an alternative for achieving ultra-low PN [2]–[6], avoiding the drawbacks of a large chip area, inter-core mismatch, and design complexity in multicore VCOs [7]–[19]. Yet, research on SR-VCOs is still limited. In [2], a cross-coupled SR-VCO was implemented in 55nm BiCMOS and achieved -138dBc/Hz PN at a 1 MHz offset from the 9.96GHz carrier and -190dBc/Hz peak FoM. However, the tail inductor occupied a large area, and the topology has yet to be proven applicable in pure CMOS technology. The prototype was further modified for a wider tuning range (TR) of 16% [3], but the FoM at a 1 MHz offset was degraded to -188dBc/Hz. In [4], a quadrature-ring SR-VCO that evolved from [5] was implemented in a pure CMOS technology. Its folded-transformer floorplan reduces the chip area by half compared to that in [5]. However, the issues of mode ambiguity, large area, reliability risk of active devices, and limited TR still exist. Furthermore, although several SR-VCO topologies have been explored in prior works, a differential SR-VCO implemented in pure CMOS is yet to be reported.