A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations

Disaggregating large systems has shown multifold advantages especially with current application trends prompting a shift towards chiplet-based architectures [1]–[3]. To meet increasing computing demands, 2.5D systems should allow greater interoperability across advanced technology nodes from multiple foundries, higher system memory capacity, higher 10 counts and scalable interconnect pitches. To further address the escalating memory capacity demands and mitigate the bandwidth bottleneck prevalent in AI applications, chiplet systems should be capable of workload-tailored configurations at assembly time. This adaptability enables optimal resource allocation and facilitates processing of voluminous datasets and complex AI computations.

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Publication Details

Published
2025-02-16
DOI
https://doi.org/10.1109/isscc49661.2025.10904798
Citations
7
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
15.89
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article

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations

Sriram K. Muthukumar, Brando Perez Esparza, James Greensky, Saransh Chhabra et al.
7 citations
VLSI and Analog Circuit Testing
15.89
article

A 300MB SRAM, 20Tb/s Bandwidth Scalable Heterogenous 2.5D System Inferencing Simultaneous Streams Across 20 Chiplets with Workload-Dependent Configurations

Sriram K. Muthukumar, Brando Perez Esparza, James Greensky, Saransh Chhabra, Esdras Juárez Hernández, Anuradha Srinivasan, Tanay Karnik, Satish Yada, Jaykant Timbadiya, Shawna M. Liff, Dan Lake, Xavier Brun, Thomas Thomas, Erika Ramirez Lozano, Leonid Azarenkov, Paolo Aseron, Prerna Budhkar, Mikhail Moiseev, Ronald Kalim, Mukesh Bhartiya, Arun Radhakrishnan, Srivatsa Srinivasa, Vinayak Honkote, Vivek De, Kamakhya Prasad Sahu, Dileep Kurian, Jainaveen Sundaram, Raül Muñoz, Alba Nydia Rubio López, Suresh Kadavakollu
article en
7 citations

Abstract

Disaggregating large systems has shown multifold advantages especially with current application trends prompting a shift towards chiplet-based architectures [1]–[3]. To meet increasing computing demands, 2.5D systems should allow greater interoperability across advanced technology nodes from multiple foundries, higher system memory capacity, higher 10 counts and scalable interconnect pitches. To further address the escalating memory capacity demands and mitigate the bandwidth bottleneck prevalent in AI applications, chiplet systems should be capable of workload-tailored configurations at assembly time. This adaptability enables optimal resource allocation and facilitates processing of voluminous datasets and complex AI computations.

Intel (United States) (US), Intel (India) (IN)
Affordable and clean energy
Openalex Percentile: Top 1%
VLSI and Analog Circuit Testing
15.89
DOISourceOpenAlex
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