An Efficient V_th-Tilting PUF Design in 3nm GAA and 8nm FinFET Technologies

This paper presents a physically unclonable function (PUF) design implemented solely with standard cells. The proposed PUF extracts entropy from process mismatches in the threshold voltages <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\text{th}})$</tex> of inverting cells. An <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{additional}\mathrm{V}_{th}$</tex> tilting scheme supports efficient PUF enrollment by screening potentially unstable responses, requiring processing only at nominal voltage/temperature (V/T) conditions. The PUF design has been implemented in 3nm GAA and 8nm FinFet technology nodes and verified on test chips across various process corners. The average bit error rate (BER) at the worst process-voltage-temperature (PVT) corner is as low as 0.3127%, enabling stable PUF key generation with a key error rate (KER) below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5.5\times 10^{-20}$</tex>, applying error corrections. Among the additional features, the power-gating scheme reduces the impact of bias-temperature instability (BT1) aging on PUF cells, the balanced sampler reduces the risk of side-channel information leakage, and laser-attack detector cells are strategically positioned near the sampling flip-flops. The PUF design, implemented solely with the standard cell library, offers significant advantages for porting to other technology nodes, while the efficient enrollment procedure reduces time and resource demands during the electrical die sorting (EDS) process for mass testing.