A Dynamically Reconfigurable Digital-Integrated Voltage-Regulator Fabric for Energy-Efficient DVFS in Multi-Domain soCs
Energy efficient SoCs frequently employ a hierarchical Voltage Regulator (VR) architecture (Fig. 8.3.1), using Buck regulators to each drive a group of Low Dropout (LDO) regulated domains. The domain with the highest <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{dd}}$</tex> requirement within each group - the critical domain - sets the voltage of its corresponding Buck rail. Such an architecture combines the complementary advantages of Buck and LDO regulators to enable efficient fine-grained Dynamic Voltage and Frequency Scaling (DVFS). Buck regulators [1]–[7] offer efficient supply-voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\text{dd}})$</tex> scaling, but they require bulky passive components which hinder integration and restrict their use to only limited numbers. In contrast, LOGs [8]–[13] are highly compact but incur significant losses due to the resistive voltage drop across their header devices. Domain grouping is performed at design time to maximize aggregate VR efficiency across the SoC, maximizing dynamic voltage scaling by the Buck regulators, while minimizing dropout losses associated with LOO <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{dd}}$</tex> conversion. Some domain groups may require combining multiple Buck converters to form multi-phase regulators for improved transient response and current compliance, ensuring regulator current limits exceed worst-case domain-group loading. SoC domains continuously undergo Power State (PState) transitions, with changing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{dd}}$</tex> and current loading. However, domain groups and Buck topologies in conventional VR architectures are immutable at run time. Restricting runtime reconfiguration precludes regrouping domains more efficiently and disaggregating multi-phase regulators (when possible) to provide more Buck regulator rails for enhanced <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{\text{dd}}$</tex> scaling efficiency.
Authors
- Visvesh Sathe (ORCID: https://orcid.org/0000-0001-7950-4495)
- Jung-Jin Park
- Julian Arenas
- Hikmet Seha Ozturk (ORCID: https://orcid.org/0000-0001-8557-5644)
- Chi-Hsiang Huang (ORCID: https://orcid.org/0000-0003-4147-4643)
- Kevin Patino-Sosa (ORCID: https://orcid.org/0000-0003-1436-5636)
Institutions
- Georgia Institute of Technology (US)
Publication Details
- Published
- 2025-02-16
- DOI
- https://doi.org/10.1109/isscc49661.2025.10904508
- Primary Topic
- Low-power high-performance VLSI design
- Type
- article
- Field-Weighted Citation Impact
- 0.00