25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS
The growing demand for higher network bandwidth has led to a significant rise in channel density within Ethernet switches and high-performance computers. As data rates continue to climb, electrical links, such as printed circuit board (PCB) traces and coaxial cables, suffer from greater defects including reflection, crosstalk, and insertion loss. Therefore, low-power and highly efficient signal integrity (SI) measurements are crucial for detecting defects in communication equipment. Traditionally, vector network analyzers (VNAs) and sampling oscilloscopes with time-domain reflectometer modules are employed for SI measurement. However, these instruments are power-hungry, expensive, and inefficient because of the limited number of ports. This work presents an integrated channel analyzer (ICA) ASIC that utilizes time-domain reflectometry (TDR) and time-domain transmission (TDT) for SI measurements. The 4-port prototype achieves a frequency range of DC to 40GHz, a rise time of 9.1 ps, and consumes only 398mW.
Authors
- Weixin Gai (ORCID: https://orcid.org/0000-0002-7162-2427)
- Bingyi Ye (ORCID: https://orcid.org/0000-0002-7671-2800)
- Haowei Niu (ORCID: https://orcid.org/0000-0002-3737-9304)
- Yuanliang Li (ORCID: https://orcid.org/0000-0002-6741-5038)
- Ruixu Wang
- Guangdong Wu (ORCID: https://orcid.org/0000-0002-2600-0493)
- Xin Liu (ORCID: https://orcid.org/0000-0001-8069-5129)
- Dunshan Yu
- Fangzhu Li
Institutions
- Peking University (CN)
Publication Details
- Published
- 2025-02-16
- DOI
- https://doi.org/10.1109/isscc49661.2025.10904730
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00