19.11 A 13GHz Charge-Pump PLL Achieving $\mathbf{15.8}\mathbf{fs}_{\mathbf{rms}}$ Integrated Jitter and -98.5dBc Reference Spur

Modern communication systems, such as RF-sampling systems utilizing wideband data converters, have imposed extremely stringent demands on phase-locked loops (PLLs) for lower jitter and spurs. Benefiting from high phase-detector (PD) gain, sub-sampling PLLs (SSPLLs) achieve superior jitter performance with low in-band phase noise (PN) [1], [2]. Nevertheless, they suffer from large reference spurs due to the binary-frequency-shift-keying (BFSK) effects (Fig. 19.11.1 top left). Sampling PLLs (SPLLs) preserve the high detection gain without periodically modulating the voltage-controlled oscillator (VCO) [3]–[5]. However, the maximum PN suppression is typically limited by the available <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$K_{\text{stope}}$</tex>, which is in turn set by the parasitic capacitor <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$C_{\mathrm{P}}$</tex> as shown in Fig. 19.11.1 (top right). Charge-pump PLLs (CPPLLs) are the most widely employed architectures due to their robust lock-acquisition performance [6], [7]. Their in-band PN, primarily determined by the CP, presents a significant challenging for CPPLLs in achieving ultra-low jitter. In this work, we propose a dual-path CPPLL incorporating the resistive-discharge time-amplifying phase-frequency detector (RD-TAPFD), series-resonance VCO (SR-VCO) with over-voltage protection, and sampling-based filter, which enables the PLL to achieve 15.8fs jitter and -98.5dBc reference spur at 13GHz.