34.1 A 65fs<sub>rms</sub>-Jitter and -272dB-FoM<sub>jitter,N</sub> 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration

A digital PLL (DPLL) using a BBPD represents the optimal architecture for designing frequency synthesizers in a nanometer-scale CMOS technology because it minimizes reliance on analog circuits that require large headroom and numerous passive components. However, designing a fractional-N DPLL with low jitter, particularly at the sub-100fs level, is highly challenging due to the diverse quantization errors (Q-errors) that are inherent in digital circuits. To mitigate these Q-errors, various techniques have been proposed [1]–[5]. Recently, a common solution has involved using a digital-to-time converter (DTC) to eliminate the Q-error of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma \mathrm{M}$</tex> [6]–[13], which is the most dominant among various Q-errors. However, the DTC itself generates additional thermal noise that is proportional to the amount of delay [14], and this becomes another major source of in-band phase noise (PN). The DTC delay consists of a dynamic delay that is tunable to cancel the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \Sigma M$</tex> Q-error and a static delay that is inevitably generated when producing the dynamic delay. To cover a wider range of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma \mathrm{M}$</tex> Q-error, the DTC must be designed with a larger dynamic delay range, and this also increases the static delay. A straightforward approach to reducing the thermal noise of the DTC is to use more power, but this inevitably degrades the overall jitter-power FoM <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$[\text{FoM}_{\text{iitter}}]$</tex> of the DPLL. This dilemma underscores the need for a new design to cancel the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma M$</tex> Q-error.

Authors

Institutions

Publication Details

Published
2025-02-16
DOI
https://doi.org/10.1109/isscc49661.2025.10904741
Citations
3
Primary Topic
Photonic and Optical Devices
Type
article
Field-Weighted Citation Impact
2.19
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration

Jaehyouk Choi, Hangi Park, Seheon Jang, Munjae Chae et al.
3 citations
Photonic and Optical Devices
2.19
article

34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration

Jaehyouk Choi, Hangi Park, Seheon Jang, Munjae Chae, Chanwoong Hwanq
article en
3 citations

Abstract

A digital PLL (DPLL) using a BBPD represents the optimal architecture for designing frequency synthesizers in a nanometer-scale CMOS technology because it minimizes reliance on analog circuits that require large headroom and numerous passive components. However, designing a fractional-N DPLL with low jitter, particularly at the sub-100fs level, is highly challenging due to the diverse quantization errors (Q-errors) that are inherent in digital circuits. To mitigate these Q-errors, various techniques have been proposed [1]–[5]. Recently, a common solution has involved using a digital-to-time converter (DTC) to eliminate the Q-error of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma \mathrm{M}$</tex> [6]–[13], which is the most dominant among various Q-errors. However, the DTC itself generates additional thermal noise that is proportional to the amount of delay [14], and this becomes another major source of in-band phase noise (PN). The DTC delay consists of a dynamic delay that is tunable to cancel the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta \Sigma M$</tex> Q-error and a static delay that is inevitably generated when producing the dynamic delay. To cover a wider range of the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma \mathrm{M}$</tex> Q-error, the DTC must be designed with a larger dynamic delay range, and this also increases the static delay. A straightforward approach to reducing the thermal noise of the DTC is to use more power, but this inevitably degrades the overall jitter-power FoM <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$[\text{FoM}_{\text{iitter}}]$</tex> of the DPLL. This dilemma underscores the need for a new design to cancel the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Delta\Sigma M$</tex> Q-error.

Seoul National University (KR)
Openalex Percentile: Top 13%
Photonic and Optical Devices
2.19
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.