19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

As data-rate requirements in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\mathrm{G}$</tex>-Advanced and future <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6\mathrm{G}$</tex> communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring higher-order modulation schemes and ever-higher throughput. Under the CMOS-limited supply voltage and power-dissipation constraints, the PN in conventional parallel-resonance (PR) LC-tank oscillators is primarily limited by the tank quality factor (Q). To continue the quest for ever-lower PN, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> oscillators can be coupled together for an effective PN reduction of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10\log(N)$</tex> (Fig. 19.4.1, top-right) [1]. However, the practical implementation of multicore oscillators is hampered by 1) mismatches between the cores, which degrades the achievable PN and figure of merit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{FoM})$</tex>, and 2) the area-intensive floorplan required when coupling many cores. Series-resonance (SR) LC oscillators have the potential to achieve ultra-low PN with a single-core configuration [2]–[4]. Nonetheless, several challenges arise when implementing this configuration in CMOS: 1) Realizing a cross-coupled oscillator core that provides current-controlled negative resistance is difficult in CMOS; although, it can be achieved in bipolar technologies with additional diodes (Fig. 19.4.1, bottom-left) to maintain the output voltage amplitude [3]; 2) four-stage inverter-based SR oscillators (Fig. 19.4.1, bottom-middle) require <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times$</tex> the power consumption and introduce additional noise from active devices to maintain the oscillation, as each series-LC tank provides a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$90^{\circ}$</tex> phase shift [4]. Both reported works burn over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300\text{mW}$</tex>.

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Published
2025-02-16
DOI
https://doi.org/10.1109/isscc49661.2025.10904613
Citations
4
Primary Topic
Acoustic Wave Resonator Technologies
Type
article
Field-Weighted Citation Impact
2.70

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article

19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

Robert Bogdan Staszewski, Teerachot Siriburanon, Kai‐Da Xu, Jiawen Chen
4 citations
Acoustic Wave Resonator Technologies
2.70
article

19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

Robert Bogdan Staszewski, Teerachot Siriburanon, Kai‐Da Xu, Jiawen Chen
article en
4 citations

Abstract

As data-rate requirements in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5\mathrm{G}$</tex>-Advanced and future <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6\mathrm{G}$</tex> communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring higher-order modulation schemes and ever-higher throughput. Under the CMOS-limited supply voltage and power-dissipation constraints, the PN in conventional parallel-resonance (PR) LC-tank oscillators is primarily limited by the tank quality factor (Q). To continue the quest for ever-lower PN, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$N$</tex> oscillators can be coupled together for an effective PN reduction of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10\log(N)$</tex> (Fig. 19.4.1, top-right) [1]. However, the practical implementation of multicore oscillators is hampered by 1) mismatches between the cores, which degrades the achievable PN and figure of merit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{FoM})$</tex>, and 2) the area-intensive floorplan required when coupling many cores. Series-resonance (SR) LC oscillators have the potential to achieve ultra-low PN with a single-core configuration [2]–[4]. Nonetheless, several challenges arise when implementing this configuration in CMOS: 1) Realizing a cross-coupled oscillator core that provides current-controlled negative resistance is difficult in CMOS; although, it can be achieved in bipolar technologies with additional diodes (Fig. 19.4.1, bottom-left) to maintain the output voltage amplitude [3]; 2) four-stage inverter-based SR oscillators (Fig. 19.4.1, bottom-middle) require <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4\times$</tex> the power consumption and introduce additional noise from active devices to maintain the oscillation, as each series-LC tank provides a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$90^{\circ}$</tex> phase shift [4]. Both reported works burn over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$300\text{mW}$</tex>.

University College Dublin (IE), King's College London (GB)
King’s College London, Science Foundation Ireland
Affordable and clean energy
Openalex Percentile: Top 11%
Acoustic Wave Resonator Technologies
2.70
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